commit 8871918f14026359808711c37392681999f46a41
from: kettenis <kettenis@openbsd.org>
date: Sat May 17 13:29:49 2025 UTC

Add GMAC related RK3528 clocks.

ok dlg@

commit - ff99cb2ffd6a96106021164a402d2118933bf0a5
commit + 8871918f14026359808711c37392681999f46a41
blob - 35a02642e7f68f754e43f3eb453bd83f87f4d578
blob + 36a115aabec98a9f35bdb1566163235e3b79fe8c
--- sys/dev/fdt/rkclock.c
+++ sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rkclock.c,v 1.92 2025/05/01 12:28:40 kettenis Exp $	*/
+/*	$OpenBSD: rkclock.c,v 1.93 2025/05/17 13:29:49 kettenis Exp $	*/
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -171,10 +171,11 @@
 #define RK3399_PMUCRU_CLKSEL_CON(i)	(0x0080 + (i) * 4)
 
 /* RK3528 registers */
-#define RK3528_CRU_PLL_CON(i)		(0x0000 + (i) * 4)
-#define RK3528_CRU_CLKSEL_CON(i)	(0x0300 + (i) * 4)
-#define RK3528_CRU_GATE_CON(i)		(0x0800 + (i) * 4)
-#define RK3528_CRU_SOFTRST_CON(i)	(0x0a00 + (i) * 4)
+#define RK3528_CRU_PLL_CON(i)		(0x00000 + (i) * 4)
+#define RK3528_CRU_CLKSEL_CON(i)	(0x00300 + (i) * 4)
+#define RK3528_CRU_GATE_CON(i)		(0x00800 + (i) * 4)
+#define RK3528_CRU_SOFTRST_CON(i)	(0x00a00 + (i) * 4)
+#define RK3528_PCIE_CRU_PLL_CON(i)	(0x20000 + (i) * 4)
 
 /* RK3568 registers */
 #define RK3568_CRU_APLL_CON(i)		(0x0000 + (i) * 4)
@@ -3192,6 +3193,11 @@ const struct rkclock rk3528_clocks[] = {
 		  RK3528_XIN24M }
 	},
 	{
+		RK3528_CLK_PPLL_125M_MATRIX, RK3528_CRU_CLKSEL_CON(60),
+		0, DIV(14, 10),
+		{ RK3528_PLL_PPLL }
+	},
+	{
 		RK3528_CCLK_SRC_EMMC, RK3528_CRU_CLKSEL_CON(62),
 		SEL(7, 6), DIV(5, 0),
 		{ RK3528_PLL_GPLL, RK3528_PLL_CPLL, RK3528_XIN24M }
@@ -3207,6 +3213,10 @@ const struct rkclock rk3528_clocks[] = {
 		{ RK3528_XIN24M }
 	},
 	{
+		RK3528_CLK_GMAC1_SRC_VPU, 0, 0, 0,
+		{ RK3528_CLK_PPLL_125M_MATRIX }
+	},
+	{
 		RK3528_CLK_I2C1, RK3528_CRU_CLKSEL_CON(79),
 		SEL(10, 9), 0,
 		{ RK3528_CLK_MATRIX_200M_SRC, RK3528_CLK_MATRIX_100M_SRC,
@@ -3249,6 +3259,8 @@ rk3528_get_frequency(void *cookie, uint32_t *cells)
 		return rk3328_get_pll(sc, RK3528_CRU_PLL_CON(8));
 	case RK3528_PLL_GPLL:
 		return rk3328_get_pll(sc, RK3528_CRU_PLL_CON(24));
+	case RK3528_PLL_PPLL:
+		return rk3328_get_pll(sc, RK3528_PCIE_CRU_PLL_CON(32));
 	case RK3528_XIN24M:
 		return 24000000;
 	default:
@@ -3315,6 +3327,10 @@ rk3528_reset(void *cookie, uint32_t *cells, int on)
 		reg = RK3528_CRU_SOFTRST_CON(26);
 		bit = 3;
 		break;
+	case RK3528_SRST_A_MAC:
+		reg = RK3528_CRU_SOFTRST_CON(28);
+		bit = 5;
+		break;
 	case RK3528_SRST_H_SDMMC0:
 		reg = RK3528_CRU_SOFTRST_CON(42);
 		bit = 9;
blob - 66a45f690c5ace07ee7d6d13ee99b0db9f018443
blob + 71bcd3fcffdd32ebbe287d57472e2f6cc8d4026b
--- sys/dev/fdt/rkclock_clocks.h
+++ sys/dev/fdt/rkclock_clocks.h
@@ -291,14 +291,17 @@
 
 #define RK3528_PLL_CPLL			1
 #define RK3528_PLL_GPLL			2
+#define RK3528_PLL_PPLL			3
 #define RK3528_CLK_MATRIX_50M_SRC	7
 #define RK3528_CLK_MATRIX_100M_SRC	8
 #define RK3528_CLK_MATRIX_200M_SRC	10
 #define RK3528_CLK_PWM0			111
 #define RK3528_CLK_PWM1			114
+#define RK3528_CLK_PPLL_125M_MATRIX	125
 #define RK3528_CCLK_SRC_EMMC		140
 #define RK3528_BCLK_EMMC		143
 #define RK3528_TCLK_EMMC		144
+#define RK3528_CLK_GMAC1_SRC_VPU	173
 #define RK3528_CLK_I2C1			221
 #define RK3528_CCLK_SRC_SDMMC0		295
 
@@ -309,6 +312,7 @@
 #define RK3528_SRST_A_EMMC		67
 #define RK3528_SRST_B_EMMC		68
 #define RK3528_SRST_T_EMMC		69
+#define RK3528_SRST_A_MAC		97
 #define RK3528_SRST_H_SDMMC0		189
 
 /*